The present invention relates generally to a method of providing extended address access to memory devices containing both redundant and main array elements in a packaged part.
The advent of electronic-fuse (e-fuse) technology makes it advantageous to test both the main and redundant memory elements of a random access memory (RAM), to their complete test specification, after being packaged in their final form. However, memory device, package pin counts and JDEC standards limit the externally addressable memory elements to those comprising the main array. These limitations make it impossible to seamlessly test both the main and redundancy arrays of an e-fuse RAM, once the memory device has been packaged, through the conventional method of externally addressing all of the memory elements in sequence and testing their ability to store and reproduce information.
Current test schemes use a two-pass, test method to independently and separately test the redundant and main memory arrays. This two-pass, test technique cannot adequately test the combined memory arrays for certain types of memory defects that occur at the boundary of the main and redundant arrays. Capacitive coupling and current leakage between elements of a memory array are two examples of these defects. To adequately detect these and other types of defects, it is necessary to sequentially address each of the cells of a memory device and perform a sequence of write and read operations on the cell. The sequential access of these memory cells must be performed throughout the continuum of the combined main and redundancy arrays.
In the past, the problem of extended address mode access has been dealt with by adding additional, external address input pins to a packaged part, by executing two pass testing, or by extensively modifying the test code of a test unit to address the redundant memory elements. The present invention supports extended address mode access of the main and redundant memory arrays, contained in a packaged part, without using additional, external address pins or extensively modifying the existing code of a test device.
The access method of the present invention will be especially valuable in the era of e-fuse repair devices. E-fuse technology allows memory defects to be repaired after the memory device has been incorporated into a packaged part. Previously, the boundary element defects that might exist in a memory device could only be detected prior to integrating the memory wafer into a packaged part. At wafer level, there are no package pin limitations. It is possible to seamlessly address and test all of the memory elements of the device because a wafer probe can make contact with all of the address pads of the memory chip.
The access method of the present invention permits all of the memory elements to be seamlessly addressed and accessed while in a packaged part form. In an embodiment of the invention, a test method is used for testing the memory elements of a device. Consistency in the test methodology between a wafer environment and a packaged part environment may be preserved, since all of the memory elements may be seamlessly and sequentially addressed and tested in both test environments. Certain defects that may exist at the boundary of the main and redundant memory arrays can be detected and effectively removed from the finished product. The value of this test method is that it: (1) reduces the likelihood that a defective device will not be detected by the post-packaging testing, (2) increases the productivity yield, and (3) reduces the production costs for manufacturing a particular yield of operational devices. These benefits are obtained without the need for incorporating additional address input lines in the packaged part or extensively modifying the code of a test unit.